1. Field of the Invention
The present invention relates to a delay regulating device for a reference signal and a feedback signal in an adaptive predistorter (APD) type distortion compensation device.
2. Description of the Related Art
When distortion compensation is performed in the APD system, delay regulation is required to control timing between a reference signal (Ref signal) and a feedback signal (FB signal).
FIG. 1 is a block diagram of a transmission board to which the distortion compensation in the APD system is applied.
The reference signal (Ref signal) is a baseband signal of a transmission signal. The reference signal is input to a multiplier 10, multiplied by a distortion compensation coefficient from a distortion compensation control unit 15, and input to a D/A converter 11. When the D/A converter converts a digital signal into an analog signal, a modulator 12 modulates the signal, and a power amplifier 12 amplifies and transmits the signal. The modulator receives a radio frequency for up-conversion from a local oscillator 14.
A reference signal is input to the distortion compensation control unit 15. The reference signal input to the distortion compensation control unit 15 is used to index a distortion compensation table. Furthermore, the reference signal is input to a clock unit delay unit 16. The reference signal is delayed by the clock unit delay unit 16 in a clock unit, and input to an adder 17 and a correlation calculating unit 18. The clock of the clock unit delay unit 16 is controlled by the correlation calculating unit 18, and an amount of delay by the clock unit delay unit 16 is controlled by controlling the clock.
The signal output from the power amplifier 12 is input to a multiplier 23 as a feedback signal (FB signal). The multiplier 23 multiplies the signal by a radio frequency from a local oscillator 24 for down-conversion. The output of the multiplier 23 is input to an A/D converter 22, and converted from an analog signal into a digital signal. The feedback signal converted into a digital signal is demodulated by a demodulator 21, and input to a delay filter 20. The delay filter 20 is typically a FIR filter, and can change the amount of delay of a signal by changing a tap coefficient. The output of the delay filter 20 is input to a negative terminal of the adder 17 and the correlation calculating unit 18. The correlation calculating unit 18 controls the phase of an oscillated wave of a numerical control oscillator 25 for inputting a periodical wave to the demodulator 21. The correlation calculating unit 18 calculates a correlation value between the reference signal and the feedback signal, and controls the clock unit delay unit 16 and the numerical control oscillator 25 such that the correlation value can be higher.
The adder 17 obtains a difference between the reference signal input to the adder 17 and the feedback signal input to the negative terminal of the adder 17, and inputs the result to the distortion compensation control unit 15 and an error calculating unit 19. The error calculating unit 19 adjusts the amount of delay of the delay filter 20 such that the output of the adder 17 can be lower. An error signal as output of the adder 17 is used for update of a distortion compensation coefficient of a distortion compensation table stored in the distortion compensation control unit 15.
The conventional adjustment of a relative amount of delay between a feedback signal and a reference signal is performed in the following two steps.    (1) adjusting in a clock unit by a correlation calculation between a reference signal and a feedback signal    (2) adjusting in 1/128 clock unit by an error calculation between a reference signal and a feedback signal
In step (1) above, a reference signal is delayed in a clock unit, and an amount of delay for the maximum correlation value between the reference signal and the feedback signal is calculated.
FIG. 2 shows the circuit for performing the correlation calculation.
In FIG. 2, the reference signal and the feedback signal are complex signals each of the signals includes an I signal and a Q signal. Assuming that the I signal of the reference signal is Ref_ich, the Q signal of the reference signal is Ref_qch, the I signal of the feedback signal is FB_ich, and the Q signal of the feedback signal is FB_qch, the calculation performed by the circuit shown in FIG. 2 is expressed by the following equations.Ref=Ref—ich+jRef—qchFB=FB—ich+jFB—qchthencorrelation value=ΣRef×FB*=Σ(Ref—ich+jRef—qch)×(FB—ich−jFB—qch)
where * indicates a complex conjugate, and j indicates an imaginary number unit. A correlation result real part integrator and a correlation result imaginary part integrator perform multiplication on a plurality of calculation results of a real part and an imaginary part of an obtained correlation value, and perform a calculation of a sum of the equations above.
FIG. 3 shows an example of a result of a correlation calculation.
FIG. 3 shows an example of a result of calculation of a correlation value by assigning various amounts of delay to a reference signal in a clock unit. A correlation value shows peaks at various amounts of delay, and shows the maximum peak value when the relative delay between the reference signal and the feedback signal shows the minimum value. Therefore, by detecting the amount of delay indicating the maximum peak value of the correlation value, the timing between the reference signal and the feedback signal can be detected.
Before performing the process in step (2) above, the amount of delay in a clock unit obtained in step (1) above is set. The correlation calculating unit 18 adjusts the phase of the demodulator 21 on the basis of the set delay. The correlation calculating unit 18 performs the phase adjustment of the demodulator 21 by calculating a phase value as follows.
By the correlation calculation, a phase value indicating the shift of the phase by the relative delay between the feedback signal and the reference signal can be acquired.
Assuming that FB signal=Ref×Aexp(−jθ),correlation value=ΣRef×FB*=ΣRef×Ref*×Aexp(jθ)=A·Σ|Ref|2exp(jθ)exp(jθ)=cos θ+j sin θthereby correlation value (real part)=A·Σ|Ref|2 cos θcorrelation value (imaginary part)=A·Σ|Ref|2 sin θ
As a result, the phase value is obtained as follows.θ=tan−1(correlation value(Qch)/correlation value(Ich))
The phase adjustment is performed to eliminate the phase difference between the reference signal and the feedback signal when the error calculation is performed in the delay regulation in step (2) above.
After performing the phase adjustment of the demodulator 21, the delay of the feedback signal is changed using a digital filter (delay filter). A tap coefficient for delay in 1/128 clock unit is prepared for the delay filter. By changing the tap coefficient, the delay of the feedback signal changes, and the optimum delay value of the reference signal and the feedback signal is obtained when a tap coefficient of the filter number indicating the minimum error value is selected.
FIGS. 4A and 4B explain a digital filter.
A digital filter is specifically a FIR filter. As shown by FIG. 4A, the digital filter includes a plurality of serially connected delay units, each multiplier for multiplying the output of each delay unit by a tap coefficient A0˜An, and an adder for adding up the output of each multiplier and outputting a result. To generate a delay in 1/128 clock unit, 128 delay units are provided. The delay value of each delay is 128 clocks.
FIG. 4B shows an example of a tap coefficient, and is a plot having a vertical axis indicating the value of each tap coefficient when there are 11 taps. Although there are various methods of setting a tap coefficient, an amount of delay depends on the setting of each tap coefficient.
FIG. 5 shows an example of a circuit for performing an error calculation, and FIG. 6 shows an example of an error calculation result.
The contents of the calculation by the error calculation circuit shown in FIG. 5 are expressed by the following equations.Ref=Ref—ich+jRef—qchFB=FB—ich+jFB—qch
Then, an error value is calculated as follows.Σ{(Ref_ich+jRef_qch)−(FB_ich−jFB_qch)}
As a result, the real part and the imaginary part of the difference are expressed as follows.error value(real part)=Σ(Ref—ich−FB—ich)error value(imaginary part)=Σ(Ref—qch−FB—qch)
An absolute value of the error value is obtained.
The name of each variable is the same as that in the description of the correlation calculation. The error result real part integrator and the error result imaginary part integrator obtain a sum of the real part and the imaginary part of the error value.
FIG. 6 shows an amount of delay of a feedback signal in 1/128 clock unit along a horizontal axis, and shows an error value along the vertical axis. The amount of delay indicating the minimum error value is the optimum amount of delay.
However, the conventional system of adjusting an amount of delay has the following problem.
The phase adjustment of the demodulator at the preceding stage of the error calculation in step (2) above is performed using the optimum point of the clock obtained in step (1) above and an initial value delay filter (initial value (0) in 1/128 clock unit), but there is the possibility that the filter tap coefficient of the optimum delay point is different from the delay filter tap coefficient of the initial value. In this case, the phase adjustment is performed with a shifted delay, a correct phase cannot be obtained, thereby failing in obtaining a correct tap coefficient.
FIG. 7 shows the phase adjustment result of the demodulator using a tap coefficient (delay value), and FIG. 8 shows variations of the delay regulation results of the error calculation.
FIG. 7 shows along the horizontal axis the number of times of performing the phase adjusting process, and shows along the vertical axis a change in phase value. The graph shows the three cases of set values of 0, 128, and 64 of the amount of delay in 1/128 clock unit. As shown by the graph, unless the tap coefficient of the delay filter is appropriate, the phase value is not close to 0 although the phase adjusting process is repeated many times.
FIG. 8 shows the case in which a delay regulation is performed using a delay filter on the basis of a result of the error calculation. FIG. 8 shows a result of repeating the trial delay regulation several times, and the graphs using different marks refer to different trials. As shown in FIG. 8, each time trial delay regulation is performed, a different amount of delay brings about the minimum error result, and the optimum reliable amount of delay cannot be obtained only by the delay regulation using an error result.
The conventional distortion compensation device can be the patent document 1. The patent document 1 discloses a technique of not updating a distortion compensation table when a phase value is abnormal.
Patent Document 1: International Patent Application Publication No. WO 03/103166